There has long been a problem with differential polishing during chemical mechanical polishing (CMP) of filled wide inset trenches, as contrasted to narrow ones, in semiconductors. Due to the abrasive nature of the slurry used, material in the center of wide trenches is abraded faster than in narrow trenches. This has gotten to be a serious problem when considering future semiconductor technology, especially if copper conductors are to be used.
Copper interconnect is believed to be the process of choice for future deep submicron semiconductor technologies. This is because of copper's low resistivity and high electromigration resistance as compared with aluminum which is currently used for interconnects. One of the key enabling elements of the copper interconnecting process is Damascene. Damascene involves inlay of copper in preformed inset trenches in the silicon dioxide dielectric layer of a semiconductor device. This is accomplished by an overall deposition of copper, followed by chemical mechanical polishing down to the surface of the silicon dioxide dielectric layer to form the copper metal interconnect wires.
A long time problem using copper interconnects has been that copper CMP along wide interconnect lines are subject to thinning out or dishing as a result of the high polishing rate in the center of wide areas. As a result, affected copper thickness will be thinner for wide lines than for narrow ones, resulting in a smaller sheet resistance and jeopardizing the integrity of interconnections for high performance device applications.
While there have been a number of different approaches to solving the dishing problem, none have provided a straight forward processing system utilizing the essential elements of standard semiconductor manufacturing techniques of photolithography and photolithographic processing.